1. Field of the Invention
The present invention relates to semiconductor devices-such as MISFETs (metal insulator semiconductor field-effect transistors) capable of suppressing threshold voltage (Vth) variations due to a short channel effect or manufacturing variations. In particular, the present invention relates to MISFETs' impurity concentration profiles including channel impurity concentration profiles and counter impurity concentration profiles.
2. Description of the Related Art
It has been warned that micronization of a MISFET increases the influence of channel impurity concentration variations on Vth variations, to deteriorate the characteristics of the MISFET.
A CMOS (complementary metal oxide semiconductor) circuit may have a pMOSFET with an n+ polysilicon gate and a counter-doped channel surface. The counter doped channel surface has an opposite conductivity type from a channel conductivity type, thereby forming a buried channel. The buried channel will suffer from a short channel effect if the counter-doped channel surface is deep. The short channel effect is a phenomenon that a threshold voltage (Vth) drops as a gate length is shortened. When micronized, the pMOSFET must have a short gate length. If the gale length is shortened to a lithography control limit a gale length variation will account for a significant part of the gate length and the short channel effect will vary the electric characteristics of the pMOSFET, to deteriorate yield of CMOS circuits. A micronized CMOS circuit must employ a low source voltage. To decrease source voltage, it is necessary to decrease the threshold voltage (Vth) of a transistor. The threshold voltage, however increases in proportion to a substrate impurity concentration, which must be high to suppress the short channel effect. Namely, increasing a substrate impurity concentration to suppress the short channel effect results in deteriorating transistor characteristics.
To solve this problem, a counter-doped layer of high impurity concentration may be formed at the surface of a substrate. This may increase a substrate impurity concentration to suppress the short channel effect. The counter-doped layer of high impurity concentration, however, must be very shallow to provide a low Vth value. It is difficult to form such a shallow, high-impurity-concentration, counter-doped layer because the counter-doped layer is inevitably thickened by thermal impurity diffusion during high-temperature processes such as a gate insulating film forming process and an impurity activation process.
As mentioned above, a buried channel is formed when a channel impurity layer is counter-doped. For example, an n-type impurity distribution having a gentle concentration profile is formed in a substrate, and p-type impurities are introduced into a shallow area of the substrate to cancel the n-type impurity distribution at the substrate surface, as disclosed by 1. C. Kizilyalli et al. in “N+-Polysilicon Gate PMOSFETs with Indium Doped Buried-Channels,” IEEE Electron Device Letters, vol. 17, pp 46–49, 1996. This technique introduces p-type counter impurities to form a shallow p-type region in a substrate. Compared with a deep profile, the shallow profile forms a channel closer to the substrate surface, to prevent an increase in the effective thickness of a gale insulating film and suppress the short channel effect. To cancel a high n-type impunity concentration around a pn junction, the p-type impurities to be introduced must be of high concentration. MOSFETs with buried channels and n+ polysilicon gales are known to involve large Vth variations.
To meet a low source voltage, nMOSFETs as well as pMOSFETs are required to have low Vth values. A low Vth value is achievable by counter doping even if a channel impurity concentration is high. MOSFETs conventionally employ polysilicon gates that involve high gale resistance to hinder micronization. The gate resistance is reducible by replacing the polysilicon gates with metal ales. The metal gales provide a high work function, and therefore, an nMOSFET having a metal gale and a buried channel will simultaneously realize a low Vth value and a high channel impurity concentration to suppress the short channel effect, as disclosed by A. Chatterjee et al. in “CMOS Metal Replacement Gale Transistors Using Tantalum Pentoxide Gate Insulator.” IEDM 98, pp 777–780, 1998. However, there are no reports that describe how to realize a low Vth value with a metal gale. It is even claimed that a surface channel is superior to a buried channel for a metal (ate because the buried channel involves large Vth variations. Namely a large problem with the metal gale is a channel impurity concentration profile.